Sigasi (@sigasi) 's Twitter Profile
Sigasi

@sigasi

Sigasi redefines the creation, integration, and validation of Hardware Design Language (HDL) specifications.

ID: 29658904

linkhttp://www.sigasi.com calendar_today08-04-2009 06:52:26

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Sigasi
@sigasi

a year ago

Sigasi 5.3 has arrived! 🔄 Update now to enjoy many new VHDL linting rules, better support for SystemVerilog parameterized classes, and more control over project-specific guidelines & conventions with new preference settings: zurl.co/BeAc #SigasiRelease #HDL #RTL

Sigasi 5.3 has arrived! 🔄 Update now to enjoy many new VHDL linting rules, better support for SystemVerilog parameterized classes, and more control over project-specific guidelines & conventions with new preference settings: zurl.co/BeAc #SigasiRelease #HDL #RTL